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1 power sequencing controllers isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 the intersil isl6123, isl6124, isl6125, isl6126, isl6127, isl6128 and isl6130 are integrated 4-channel controlled-on/controlled-off power-supply sequencers with supply monitoring, fault protecti on and a ?sequence completed? signal (reset ). for larger systems, more than four supplies can be sequenced by simply connecting a wire between the sysreset pins of cascaded ics. the isl6125 uses four open-drain outputs to control the on/off sequencing of four supplies. the other sequencers use a patented, micropower 7x charge pump to drive four external low-cost nfet switch gates above the supply rail by 5.3v. thes e ics can be biased from 5v down to 1.5v by any supply. the 4-channel isl6123 (enable input), isl6124 (enable input) and isl6125 offer the designer 4-rail control when all four rails must be in minimal compliance before turn-on and during operation. the isl6123 and isl6130 have a low-power standby mode when disabled, which is suitable for battery-powered applications. the isl6125 operates like the isl6124, but instead of charge-pump-driven gate drive outputs, it has open-drain logic outputs for direct interface to other circuitry. in contrast, for the isl6126 and isl6130, each of the four channels operates independently. each gate turns on once its individually associated input voltage requirements are met. the isl6127 is a pre-programmed a-b-c-d turn-on and d-c-b-a turn-off sequenced ic. once all inputs are in compliance and enable is asserted, sequencing be gins. each subsequent gate turns on after the previous one turns on. the isl6128 has two groups of two channels, each with its independent i/o. it is ideal for voltage sequencing into redundant capability loads. all four inputs must be satisfied before turn-on, but a single group fault is ignored by the other group. external resistors provide flexible voltage threshold programming of monitored rail voltages. delay and sequencing are provided by external capacitors for ramp-up and ramp-down. additional i/o is provided for indicating and driving the reset state in various configurations. for volume applications, othe r programmable options and features are available. contact intersil sales support with your needs. features ? enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7v to 5v) ? operates from 1.5v to 5v supply voltage ? supplies v dd +5.3v of charge pumped gate drive ? adjustable voltage slew rate for each rail ? multiple sequencers can be da isy-chained to sequence an infinite number of independent supplies ? glitch immunity ? undervoltage lockout for each supply ? 1a sleep state (isl6123, isl6130) ? active high (isl6123, isl6130) enable or low (isl6124, isl6125, isl6126, isl6127, isl6128) enable input ? open drain version available (isl6125) ? voltage-determined sequence (isl6126, isl6130) ? pre-programmed sequence available (isl6127) ? dual channel groupings (isl6128) ?qfn package ? pb-free (rohs-compliant) applications ? graphics cards ? fpga/asic/microprocessor/powerpc supply sequencing ?network routers ? telecommunications systems figure 1. typical isl6123 application aout ain bin cin din bout cout dout uvlo_b uvlo_a uvlo_d uvlo_c ain dly_on_a dly_off_a dly_off_b dly_off_c dly_off_d dly_on_b dly_on_c dly_on_d enable sysrst ground bin cin din reset v dd gate d gate c gate b gate a caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2001, 2003-2008, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. august 25, 2011 fn9005.11
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 2 fn9005.11 august 25, 2011 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package pkg. dwg. # isl6123irza 61 23irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6124irza 61 24irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6125irza 61 25irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6126irza 61 26irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6127irza 61 27irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6128irza 61 28irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6130irza 61 30irz -40 to +85 24 ld 4x4 qfn l24.4x4 isl6123eval1z isl6123 evaluation platform isl6125eval1z isl6125 evaluation platform notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6123, isl6124 , isl6125 , isl6126 , isl6127 , isl6128 , isl6130 . for more information on msl please see tech brief tb363 . figure 2. typical isl6123 application usage figure 3. isl6123 block diagram (1/4) aout ain bin cin din bout cout dout uvlo_b uvlo_a uvlo_d uvlo_c ain dly_on_a dly_off_a dly_off_b dly_off_c dly_off_d dly_on_b dly_on_c dly_on_d enable sysrst ground bin cin din reset v dd gate d gate c gate b gate a en sysrst uvlox 0.633v reset dly_onx 1.26v dly_offx 1.26v gatex logic 1a bias lock out vdd rising delay vdd+5v q-pump 1a 1a -1a 30s filter 150ms rising delay 10ms
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 3 fn9005.11 august 25, 2011 pin configurations isl6123, isl6124, isl6125 (24 ld qfn) top view isl6126, isl6130 (24 ld qfn) top view isl6127 (24 ld qfn) top view isl6128 (24 ld qfn) top view 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 epad enable_1/ enable_1 gate_a dly_off_c dly_off_d gate_b gate_c gate_d dly_on_b nc gnd uvlo_b dly_off_b uvlo_d dly_on_d dly_on_c uvlo_c dly_off_a nc uvlo_a dly_on_a sysrst vdd reset (gnd) nc 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 epad enable_1/ enable_1 gate_a dly_off_c dly_off_d gate_b gate_c gate_d nc nc gnd uvlo_b dly_off_b uvlo_d nc nc uvlo_c dly_off_a nc uvlo_a nc nc vdd reset (gnd) nc 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 epad enable_1/ enable_1 gate_a nc nc gate_b gate_c gate_d nc nc gnd uvlo_b nc uvlo_d nc nc uvlo_c nc nc uvlo_a nc sysrst vdd reset (gnd) nc 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 epad enable _1 gate_a dly_off_c dly_off_d gate_b gate_c gate_d dly_on_b reset _2 gnd uvlo_b dly_off_b uvlo_d dly_on_d dly_on_c uvlo_c dly_off_a nc uvlo_a dly_on_a nc vdd reset (gnd) enable _2
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 4 fn9005.11 august 25, 2011 pin descriptions pin name pin number description isl6123, isl6124, isl6125 isl6126, isl6130 isl6127 isl6128 vdd 23 23 23 23 chip bias. bias ic from nominal 1.5v to 5v. gnd 10 101010bias return. ic ground. enable_1/ enable _1 1 1 1 1 input to start on/off sequencing. input to initiate start of programmed sequencing of supplies on or off. enable functionality disabled for 10ms after uvlo is satisfied. isl6123 and isl6130 have enable, and isl6124, isl6125, isl6126 and isl6127 have enable . only isl6128 has two enable inputs; one for each 2-channel grouping. enable _1 is for (a, b), and enable _2 is for (c, d). enable_2/ enable _2 nc nc nc 11 reset 24 24 24 24 reset output. reset provides low signal 150ms after all gates are fully enhanced. delay is for stabilizat ion of output voltages. reset asserts low upon uvlo not being satisfied or enable/enable being deasserted. reset outputs are open-drain, n-channel fet and are guaranteed to be in correct state for vdd down to 1v and are filtered to ignore fast transients on vdd and uvlo_x. reset _2 only exists on isl6128 for (c, d) group i/o. reset _2 nc nc nc 9 uvlo_a 20 20 20 20 undervoltage lockout/monitoring input. provides a programmable uv lockout referenced to an internal 0.633v reference. filtered to ignore short (<30s) transients below programmed uvlo level. uvlo_b 12 12 12 12 uvlo_c 17 17 17 17 uvlo_d 14 14 14 14 dly_on_a 21 - - 21 gate on delay timer output. a llows programming of de lay and sequence for vout turn-on using a capacitor to ground. each capacitor charged with 1a 10ms after turn-on initiated by enable/enable . internal current source provides delay to associated fet gate turn-on. dly_on_b 8 - - 8 dly_on_c 16 - - 16 dly_on_d 15 - - 15 dly_off_a 18 18 - 18 gate off delay timer output. allows programming of delay and sequence for vout turn-off through enable/enable via a capacitor to ground. each capacitor charged with 1a internal current source to an internal reference voltage, causing corresponding gate to be pulled down, thus turning off fet. dly_off_b 13 13 - 13 dly_off_c 3 3 - 3 dly_off_d 4 4 - 4 gate_a 2 2 2 2 fet gate drive output. drives external fets with 1a current source to soft- start ramp into load. on isl6125 only, these are open drain outputs that can be pulled up to a maximum of vdd voltage. gate_b 5 5 5 5 gate_c 6 6 6 6 gate_d 7 7 7 7 sysrst 22 - 22 - system reset i/o. as an input, allows for immediate and unconditional latch-off of all gate outputs when driven low. th is input can also be used to initiate programmed sequence with ?zero? wait (no 10ms stabilization delay) from input signal on this pin being driven high to first gate. as an output, when there is a uv condition, this pin pulls low. if common to other sysrst pins in a multiple ic configuration, it causes immediate and un conditional latch-off of all other gates on all other isl612x sequencers. gnd epad epad epad epad ground. die substrate nc 9, 19 8, 9, 11, 15, 16, 19, 21, 22 3, 4, 8, 9, 11, 13, 15,16,18, 19, 21 19, 22 no connect
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 5 fn9005.11 august 25, 2011 isl612x and isl6130 variant feature matrix part name en/en cmos/ ttl gate drive or open drain outputs required conditions for initial start-up number of uvlo inputs monitored by each reset number of channels that turn off when one uvlo faults preset or adjustable sequence number of uvlo and pairs of i/o features isl6123 en ttl gate drive 4 uvlo 1 en 4 uvlo 4 gates time adjustable on and off 4 monitors with 1 i/o auto restart, low bias current sleep isl6124 en cmos gate drive 4 uvlo 1 en 4 uvlo 4 gates time adjustable on and off 4 monitors with 1 i/o auto restart isl6125 en cmo open drain 4 uvlo 1 en 4 uvlo 4 open drain time adjustable on and off 4 monitors with 1 i/o auto restart, open drain sequenced outputs isl6126 en cmos gate drive 1 uvlo 1 en 4 uvlo 1 gate voltage determined on time adjustable off 4 monitors with 1 i/o gates independent on as uvlo valid isl6127 en cmos gate drive 4 uvlo 1 en 4 uvlo 4 gates preset 4 monitors with 1 i/o auto restart isl6128 en cmos gate drive 4 uvlo 2 en 2 uvlo 2 gates preset 2 monitors with 2 i/o dual redundant operation isl6130 en ttl gate drive 1 uvlo 1 en 4 uvlo 1 gate voltage determined on time adjustable off 4 monitors with 1 i/o gates independent on as uvlo valid low bias current sleep
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 6 fn9005.11 august 25, 2011 absolute maximum ratings (note 6) thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +6v isl6125 logic out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v uvlo, enable, enable , sysrst . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v reset , dly_on, dlyoff . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.5v to +5.5v temperature range ( t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 24 ld 4x4 qfn package (notes 4, 5) . . . . . 46 8 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 1.5v to +5v, t a = t j = -40 c to + 85 c , unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 7) typ max (note 7) unit uvlo falling undervoltage lockout threshold v uvlovth t j = +25c 619 633 647 mv undervoltage lockout threshold tempco tc uvlovth 40 v/c undervoltage lockout hysteresis v uvlohys 10 mv undervoltage lockout threshold range ruvlovth max v uvlovth - min v uvlovth 7mv undervoltage lockout delay t uvlodel enable satisfied 10 ms transient filter duration t fil v dd , uvlo, enable glitch filter 30 s delay on/off delay charging current dly_ichg v dly = 0v 0.92 1 1.08 a delay charging current range dly_ichg_r dly_ichg(max) - dly_ichg(min) 0.08 a delay charging current temperature coefficient tc_dly_ichg 0.2 na/c delay threshold voltage dly_vth 1.238 1.266 1.294 v delay threshold voltage temperature coefficient tc_dly_vth 0.2 mv/c enable/enable , reset and sysrst i/o enable threshold v enh 1.2 v enable threshold v enh 0.5 v dd v enable/enable hysteresis v enh - v enl measured at v dd = 1.5v 0.2 v enable/enable lockout delay t delen_lo uvlo satisfied 10 ms enable/enable input capacitance cin_en 5 pf reset pull-up voltage vpu_rst v dd v reset pull-down current i rst pd1 v dd = 1.5v, rst = 0.1v 5ma i rst pd3 v dd = 3.3v, rst = 0.1v 13 ma i rst pd5 v dd = 5v, rst = 0.1v 17 ma
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 7 fn9005.11 august 25, 2011 descriptions and operation the isl612x sequencer family co nsists of several 4-channel voltage sequencing controller s in various functional and personality configurations. a ll are designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. individual voltage rails are gated on and off by external n-channel mosfets, the gates of which are driven by an internal charge pump to v dd + 5.3v (vqp) in a user-programmed sequence. with the 4-channel isl6123, enable must be asserted high, and all four voltages to be sequenced must be above their respective user-programmed un dervoltage lockout (uvlo) levels before programmed output turn-on sequencing can begin. sequencing and delay are determined by the choice of external capacitor values on the dly_on and dly_off pins. reset delay after gate high t rst del gate = v dd +5v 160 ms reset output low v rst l measured at v dd = 5v with 5k pull-up resistors 0.1 v reset output capacitance c out_rst 10 pf sysrst pull-up voltage vpu_srst v dd v sysrst pull-down current ipu_1.5 v dd = 1.5v 5 a ipu_5 v dd = 5v 100 a sysrst low output voltage vol_srst v dd = 1.5v, i out = 100a 150 mv sysrst output capacitance cout_srst 10 pf sysrst low to gate turn-off t delsys_g gate = 80% of v dd + 5v 40 ns gate gate turn-on current i gateon gate = 0v 0.8 1.1 1.4 a gate turn-off current i gateoff_l gate = v dd , disabled -1.4 -1.05 -0.8 a gate current range i gate_range within ic i gate max-min 0.35 a gate turn-on/off current temperature coefficient tc_i gate 0.2 na/c gate pull-down high current i gateoff_h gate = v dd , uvlo = 0v 88 ma gate high voltage v gateh v dd < 2v, t j = +25c v dd + 4.9v v v gateh v dd > 2v v dd + 5v v dd + 5.3v v gate low voltage v gatel gate low voltage, v dd = 1v 0 0.1 v isl6125 open drain open drain on resistance r dson_5v v dd = 5v, en = v dd 25 r dson_3.3v v dd = 3.3v, en = v dd 32 r dson_2.5v v dd = 2.5v, en = v dd 40 bias ic supply current i vdd_5v v dd = 5v 0.20 0.5 ma i vdd_3.3v v dd = 3.3v 0.14 ma i vdd_1.5v v dd = 1.5v 0.10 ma isl6123, isl6130 stand by ic supply current i vdd_sb v dd = 5v, enable = 0v 1 a v dd power-on reset v dd _por 1 v note: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v dd = 1.5v to +5v, t a = t j = -40 c to + 85 c , unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) unit
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 8 fn9005.11 august 25, 2011 once all four uvlo inputs and enable are satisfied for 10ms, the four dly_on capacitors ar e simultaneously charged with 1a current sources to the dly_vth level of 1.27v. as each dly_on pin reaches the dly_vth level, its associated gate turns on, with a 1a source current to the vqp voltage of v dd + 5.3v. thus, all four gates se quentially turn on. once at dly_vth, the dly_on pins discharge so they are ready when next needed. after the entire turn-on sequen ce has been completed and all gates have reached the charge pumped voltage (vqp), a 160ms delay is started to ensure stability, after which the reset output is released to go high. after turn-on, if any input falls below its uvlo point for longer than the glitch filter period (~30s), it is considered a fault. reset and sysrst are pulled low, and all gates are simultaneously also pulled low. in this mode, the gates are pulled low with 88ma. normal shutdown mode is entered when no uvlo is violated and enable is deasserted. when enable is deasserted, reset is asserted and pulled low. next, all four shutdown ramp capacitors on the dly_of f pins are charged with a 1a source. when any ramp-capacitor reaches dly_vth, a latch is set, and a current is sunk on the respective gate pin to turn off its external mosfet. when the gate voltage is approximately 0.6v, the gate is pulled down the rest of the way at a higher current level. ea ch individual external fet is thus turned off, which removes the voltages from the load in the programmed sequence. the isl6123 and isl6124 have the same functionality, except for the enable active polarity; the isl6124 has an enable input. additionally, the isl6123 and isl6130 also have an ultra low-power sleep state when enable is low. the isl6125 has the same personality as the isl6124, but instead of charged-pump-driven gate outputs, it has open-drain outputs that can be pulled up to a maximum of vdd. the isl6126 and isl6130 are different in that their on sequence is not time determined but voltage determined. each of the four channels operates independently. once the ic is biased and any one of th e uvlo inputs is greater than the 0.63v internal reference, the enable input is also satisfied. the gate for the associated uvlo input turns on. in turn, the other uvlo inputs must be satisfied for the associated gates to turn on. for a period of 150ms after all gates are fully on (gate voltage = vqp), reset is released to go high. the uvlo inputs can be driven by either a previously turned-on output rail offering a voltage-determined sequence or by logic signal inputs. any subsequent uvlo level that is less than its programmed level pulls the associated gate and reset output low (if previously released) but does not latch-off the other gates. predetermined turn-off is accomplished by deasserting enable. this causes reset to latch low and all four gate outputs to follow the programmed turn-off sequence, similarly to the isl6124. the isl6127 is a 4-channel sequencer pre-programmed for a-b-c-d turn-on and d-c-b-a turn-off. after all four uvlo and enable inputs are satisfied for ~10ms, the sequencing starts. the next gate in the sequence starts to ramp up once the previous gate has reached ~vqp-1v. after a period of 160ms after the last gate is at vqp, the reset output is deasserted. if any uvlo is unsatisfied, reset is pulled low, sysrst is pulled low, and all gates are simultaneously turned off. when enable is signaled high, the d gate starts to pull low. once below 0.6v, the next gate starts to pull low, and so on, until all gates are at 0v. unloaded, this turn-off sequence completes in <1ms. this variant offers a lower cost and size implementation because the external delay capacitors are not used. because the delay capacitors are not used, this ic cannot delay the start of subsequent gates. thus, necessary stabilization or system housekeeping need to be considered. the isl6128 is a 4-channel device that groups the four channels into two groups of two channels each. each group of a, b and c, d, has its own enable and reset i/o pins. all four uvlo and both enable s must be satisfied for sequencing to start. the a, b group turns on first, 10ms after the second enable is pulled low, with a then b turning on, followed by c then d. once the preceding gate = vqp, the next dly_on pin starts to charge its capacitor; thus, all four gates turn on. approximately 160ms after d gate = vqp, the reset output is released to go high. once any uvlo is unsatisf ied, only the related group?s reset and two gates are pulled low. the related en input must be cycled for the faulted group to be turned on again. normal shutdown is invoked by signaling both enable inputs high, which causes the two related gates to shut down in reverse order from turn-on. dly_x capacitors adjust the delay between gates during turn-on and turn-off, but not the order. during bias up, the reset output is guaranteed to be in the correct state, with vdd lower than 1v. upon power-up, the sysrst pi n follows vdd with a weak internal pull-up. it is both an input and an output connection and can provide two functions. as an input, if it is pulled low, all gates are unconditionall y shut off, and reset pulls low (figure 8). this input can also be used as a no-wait enabling input. if all inputs (enable and uvlo) are satisfied, it does not wait through the ~10ms enable delay to initiate dly_on capacitor charging when released to go high. as an output, it is useful when implementing multiple sequencers in a design needing simultaneous sh utdown, as with a kill switch across all sequencers. once any uvlo is unsatisfied longer than tfil, the related sysrst pulls low. it also pulls low all other sysrst inputs that are on a common connection. by doing so, it unconditionally shuts down a ll outputs across multiple sequencers. except for the isl6128 after a fault, restart of the turn-on sequence is automatic, once al l requirements are met. this allows for no interaction between the sequencer and a controller ic, if desired. the enable and reset i/o do allow for a higher level of feedback and control, if desired. the isl6128 requires that the related enable be cycled for restart of its associated group gates. if no capacitors are connected between dly_on or dly_off pins and ground, then all such related gates start to turn on immediately after the 10ms (tuvlodel) enable stabilization timeout has expired. the gates start to turn off immediately when enable is asserted.
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 9 fn9005.11 august 25, 2011 if some of the rails are sequence d together to reduce cost and eliminate the effect of capacitor variance on the timing, a common capacitor can be connected to two or more dly_on or dly_off pins. in this case, mult iply the capacitor value by the number of common dly_x pins to obtain the desired timing. table 1 shows the nominal time delay on the dly_x pins for various capacitor values, from the start of charging to the 1.27v reference. this table does no t include the 10ms of enable lockout delay during a start-up sequence, but it does represent the time from the end of the en able lockout delay to the start of gate transition. there is no enable lockout delay for a sequence-off, so this table illustrates the delay to gate transition from a disable signal. figure 4 shows the turn-on and figure 5 shows the nominal turn-off timing diagram of the isl6123 and isl6124. the isl6125 is similar to the isl6124 except that, instead of charge pumped gate outputs, there are sequenced open-drain outputs that can be pulled up to a maximum of vdd. delay and flexible sequencing possibilities include multiple series, parallel, or adjustable capacitors that can be used to easily fine-tune timing over that offered by standard value capacitors. table 1. nominal delay to sequencing threshold dly pin capacitance time(s) open 0.00006 100pf 0.00013 1000pf 0.0013 0.01f 0.013 0.1f 0.13 1f 1.3 10f 13 note: nom. t del_seq = capacitor (f)*1.3m . figure 4. isl6123, isl6124 turn-on and glitch response timing diagram uvlo_b uvlo_c uvlo_d enable (isl6123) reset dlyon_a dlyon_b dlyon_c dlyon_d gate_a gate_b gate_c gate_d uvlo_a v en dly_vth dly_vth dly_vth dly_vth v qpump v qpump v qpump enable (isl6124) v uvlovth v uvlovth v uvlovth v uvlovth t rstdel t uvlodel v qpump -1v v qpump isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 10 fn9005.11 august 25, 2011 l figure 5. isl6123, isl6124 turn-off timing diagram enable (isl6124) reset dlyoff_a dlyoff_b dlyoff_c dlyoff_d gate_d gate_c gate_b gate_a enable (isl6123) v en uvlo_x>vuvlovth dly_vth dly_vth dly_vth dly_vth typical performance curves figure 6. uvlo threshold voltage figure 7. dly charge current 634 633 632 631 628 626 uv threshold (mv) temperature (c) 627 -40 0 20 60 -20 40 80 100 630 629 v dd = 5v v dd = 1.5v dly current source (a) -40 0 20 60 -20 40 80 100 temperature (c) 1.03 1.02 0.97 0.98 0.99 1.00 1.01 1.04 dly_off/on v dd = +5v v dd = 1.5v
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 11 fn9005.11 august 25, 2011 using the isl6123eval1z platform the isl6123eval1z platform layout illustrates the small implementation size for a typical 4-rail sequencing application. the platform allows evaluation of the isl6123, isl6124, isl6126, isl6127, isl6128 and isl6130. see figure 17 for schematic and photograph of evaluation platform and table 2 for the component listing. significant current loading of the gate or capacitive loading of the dly_on and off pins will affect functionality and performance. the default configuration of the isl6123eval1z circuit is built around the following design assumptions: 1. using the isl6123ir. 2. the four supplies being sequenced are 5v (in_a), 3.3v (in_b), 2.5v (in_d) and 1.5v (in_c). the uvlo levels are ~80% of nominal voltages. resistors are chosen such that the total resistance of each divider is ~ 10k. using standard value resistors to approximate 80% of nominal voltage supply = 0.63v on uvlo input. 3. the desired order turn-on sequence is 5v first, then 3.3v about 12ms later, then the 2.5v supply about 19ms later, and lastly, the 1.5v supply about 40ms later. 4. the desired turn-off sequence is first both 1.5v and 3.3v supplies at the same time, then the 2.5v supply about 50ms later, and lastly, the 5v supply about 72ms after that. led off indicates sequence has completed and reset has released and pulled high. the board is shipped with the isl6123 installed and with each of the other released variant types loose packed. as this sequencer family has a common function pinout for most variants, no major modifications to the board are necessary to evaluate the other ics. see figure 18 for the isl6125-specific evaluation board and schematic. all scope shots are taken from the isl6123eval1z board. figures 9 and 10 illustrate the desired turn-on and turn-off sequences, respectively. the sequencing order and delay between voltages sequencing is set by external capacitance values; sequences other than those illustrated can be accomplished. figures 11 and 12 illustrate the timing relationships between the en input; the reset , dly and gate outputs; and the vout voltage for a single channel being turned on and off, respectively. reset is not shown in figure 11 as it asserts 160ms after the last gate goes high. all ic family variants share a si milar function for dly_x capacitor charging and gate and reset operation. figures 13 through 16 illustrate the principal feature and functional differences for each of the isl6125, isl6126, isl6127 and isl6128 variants. figure 13 shows the isl6125 open-drain outputs being sequenced on and off, along with the reset relationship, which is similar to all other family variants. figure 14 illustrates the inde pendent input feature of the isl6126 which, once en is low, allows for each uvlo to be individually satisfied and for its associated gate to turn on. only when the last variable vin is satisfied, as shown, does reset release, to signal all input voltages are valid. figure 15 shows the isl6127 pre-programmed abcd turn-on and dcba turn-off order of sequencing, with minimal non-adjustable delay between each. figure 16 demonstrates the independence of the isl6128, the redundant 2-rail sequencer. it shows that either one of the two groups can be turned off, and the abcd order of restart with capacitor programmable delay, once both en inputs are pulled low. figure 8. sysrst low to output latch-off typical performance curves (continued) 1s/div 5vout gate sysrst 2v/div 3.3vout
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 12 fn9005.11 august 25, 2011 using the isl6125eval1z platform the isl6125eval1z is the isl6125-specific evaluation board that allows evaluation of the isl6125 and the isl6130 with their open-drain outputs (contact intersil sales support with your needs). the uvlo levels, sequence and delays are programmed exactly like the othe r isl612x ics except that the isl6125 and isl6130 have sequenced, open-drain outputs rather than charge-pump-driven gate outputs. see figure 18 for the isl6125eval1z schematic and photograph and table 3 for the component listing. typical performance waveforms figure 9. isl6124 sequenced turn-on f igure 10. isl6124 sequenced turn-off figure 11. isl6123 single channel turn-on f igure 12. isl6123 single channel turn-off 1v/div 40ms/div 5vout 3.3vout 2.5vout reset enable 1.5vout 1v/div 20ms/div 5vout 3.3vout 2.5vout 1.5vout enable 10ms/div gate 2v/div dly_vth en 2v/div dly_on 1v/div 3.3vo 1v/div t delenlo 4ms/div 3.3vo 1v/div reset 2v/div gate 2v/div en 2v/div dly_off 1v/div dly_vth
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 13 fn9005.11 august 25, 2011 figure 13. isl6125 logic outputs sequenced on and off and reset relationship figure 14. isl6126 uvlo input/output independence and reset relationship figure 15. isl6127 pre-programmed abcd turn-on and dcba turn-off figure 16. isl6128 group independent turn-off and delay adjustable pre-programmed turn-on typical performance waveforms (continued) en reset 100ms/div logic a -d sequenced outputs vin_var reset 100ms/div trstdel vout_var static en/all other vout a_vout b_vout c_vout d_vout b_vout c_vout d_vout a_vout en _2 5v/div en _1 5v/div
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 14 fn9005.11 august 25, 2011 1.5v 2.5v 3.3v +5v c1 1f c2 0.01f 0.1f 0.01f 0.068f c4 c5 c3 c7 0.047f c8 0.01f c6 0.01f c9 0.1f nc sysrst gnd reset 1 reset 2 gate_d gate_c gate_b gate_a isl6123ir uvlo_a dly_off_b uvlo_c uvlo_d uvlo_b dly_off_c dly_off_d dly_on_a s1 dly_on_d dly_on_c dly_on_b v dd en_2 en_1 4.99k 1.47k 3.01k r12 r5 en1 en2 r1 r2 r4 r6 7.68k 6.98k 8.45k 12 14 17 20 22 19 r9 dnp r10 750 2 5 6 7 sysrst 4 3 13 18 21 15 16 8 23 q1 2 7 1 4 q1 5 7 8 r9 10 r10 10 r13 10 r14 10 4 2 1 6 8 3 6 q2 dly_off_a r3 r11 10 1 11 9 24 2.26k figure 17. isl6123eval1z schematic and photograph 5 3 q2 4.99k z d1 d2 dnp rst rst2 ep 25
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 15 fn9005.11 august 25, 2011 4.99k r6 1.5v_(inc) 2.5v_(ind) 7.68k r2 6.98k r4 4.99k 1.47k 14 u1 21 1f 20 r12 isl6125 17 11 10 r5 seq_d seq_a r10 r8 c8 c9 c6 c4 c7 c3 c2 d1 r7 r3 r11 c1 open 0.1f 0.01f open 0.01f 0.047f 2.26k 3.01k 10k 10k 10k 750 0.022f 0.068f c5 r1 8 15 16 3 4 13 18 2 5 6 24 25 9 12 1 23 r9 10k seq_b seq_c 19 r13 7 22 gate_c gate_b gate_a dly_off_a dly_off_b dly_off_d dly_off_c dly_on_d dly_on_b v dd uvlo_b uvlo_d uvlo_c uvlo_a ep gnd dly_on_c dly_on_a gate_d nc nc sysrst enable reset a a 3.3v_(inb) 5.0v_(ina) 8.45k 21 reset agnd sysrst enable r2 figure 18. isl6125eval1z schematic and photograph
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 16 fn9005.11 august 25, 2011 table 2. isl6123eval1z board component listing component designator component function component description u1 isl6123 intersil, isl6123, four supply sequencer q1, q2 voltage rail switches fds6990s or equivalent, dual n-channel mosfet r6 5v to uvlo_a resistor for divider string 8.45k 1%, 0402 r11 uvlo_a to gnd resistor for divider string 1.47k 1%, 0402 r1 3.3v to uvlo_b resistor for divider string 7.68k 1%, 0402 r12 uvlo_b to gnd resistor for divider string 2.26k 1%, 0402 r2 2.5v to uvlo_d resistor for divider string 6.98k 1%, 0402 r3 uvlo_d to gnd resistor for divider string 3.01k 1%, 0402 r4 1.5v to uvlo_c resistor for divider string 4.99k 1%, 0402 r5 uvlo_d to gnd resistor for divider string 4.99k 1%, 0402 r9 reset led current limiting resistor 750 10%, 0402 c5 5v turn-on delay capacitor a (~10ms) dnp, 0402 c9 5v turn-off delay capacitor a (~140ms) 0.1f 10%, 6.3v, 0402 c2 3.3v turn-on delay capacitor b (~13ms) 0.01f 10%, 6.3v, 0402 c8 3.3v turn-off delay capacitor b (~13ms) 0.01f 10%, 6.3v, 0402 c3 2.5v turn-on delay capacitor d (~25ms) 0.022f 10%, 6.3v, 0402 c7 2.5v turn-off delay capacitor d (0ms) dnp, 0402 c4 1.5v turn-on delay capacitor c (~100ms) 0.068f 10%, 6.3v, 0402 c6 1.5v turn-off delay capacitor c (~60ms) 0.047f 10%, 6.3v, 0402 c1 decoupling capacitor 1f, 0402 d1 reset indicating led 0805, smd leds red d2 reset indicating led dnp r9 5v load resistor 10 20%, 3w r10 3.3v load resistor 10 20%, 3w r13 2.5v load resistor 10 20%, 3w r14 1.5v load resistor 10 20%, 3w test points labeled as to function
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 17 fn9005.11 august 25, 2011 application implementations multiple sequencer implementations the isl6123, isl6124, isl6125 and isl6127 devices can be configured to control sequencing of more than four voltages. a particular configuration may be pr eferable to another, depending on concerns. the fundamental questions to determine which configuration is best suited for your applications are: 1. what level of voltage assurance is needed prior to sequencing on, and can the voltage supplies be grouped into high and low criticality? 2. is there a critical maximum time window in which all supplies must be present at load, or is there a first and a second group preference, possibly with some work done in between the two groups of voltages being present? three configurations are desc ribed and illustrated here. in applications for which the integr ity of critical voltages must be assured prior to sequencing, additi onal monitoring of the critical supplies is needed. if voltage compliance is critical for either undervoltage or overvoltage, voltage supervisors can be used to provide this additional assurance across multiple sequencers. figure 19 is a block diag ram of a voltage-compliant, high-assurance, low-risk configuration showing the isl6131 or isl6132 supervisor and a mix of fet switched outputs and logic output sequencers (isl6124 and isl6125 ics). table 3. isl6125eval1z component listing component designator component function component description u1 isl6125, four supply sequencer intersil, isl6125, four supply sequence r with open drain outputs r6 5v to uvlo_a resistor for divider string 8.45k 1%, 0402 r12 uvlo_a to gnd resistor for divider string 1.47k 1%, 0402 r1 3.3v to uvlo_b resistor for divider string 7.68k 1%, 0402 r11 uvlo_b to gnd resistor for divider string 2.26k 1%, 0402 r2 2.5v to uvlo_d resistor for divider string 6.98k 1%, 0402 r3 uvlo_d to gnd resistor for divider string 3.01k 1%, 0402 r4 1.5v to uvlo_c resistor for divider string 4.99k 1%, 0402 r5 uvlo_d to gnd resistor for divider string 4.99k 1%, 0402 r9 reset led current limiting resistor 750 10%, 0805 c5 5v turn-on delay capacitor a dnp, 0402 c9 5v turn-off delay capacitor a (135ms) 0.1f 10%, 6.3v, 0402 c2 3.3v turn-on delay capacitor b (13.7ms) 0.01f 10%, 6.3v, 0402 c8 3.3v turn-off delay capacitor b (13.7ms) 0.01f 10%, 6.3v, 0402 c3 2.5v turn-on delay capacitor d (28ms) 0.022f 10%, 6.3v, 0402 c7 2.5v turn-off delay capacitor d dnp, 0402 c4 1.5v turn-on delay capacitor c (98ms) 0.068f 10%, 6.3v, 0402 c6 1.5v turn-off delay capacitor c (59ms) 0.047f 10%, 6.3v, 0402 c1 decoupling capacitor 0.1f, 0805 d1 reset 1 indicating led 0805, smd led r8 seq_output_a pull-up resistor 10 k , 0402 r9 seq_output_b pull-up resistor 10 k , 0402 r10 seq_output_c pull-up resistor 10 k , 0402 r13 seq_output_d pull-up resistor 10 k , 0402
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 18 fn9005.11 august 25, 2011 if the mere presence of some vo ltage potential is adequate prior to sequencing on, then a small number of standard logic and gates can be used to accomplish this. the block diagram in figure 20 illustrates this vo ltage presence configuration. in either case, the sequencing is straightforward across multiple sequencers, as all dly_on capacitors simultaneously start charging ~10ms after the comm on enable input signal is delivered. this allows the choice of capacitors to be related to each other and is no different than using a single sequencer. when the common enabling signal is de-asserted, these configurations execute the turn-off sequence across all sequencers as programmed by the dly_off capacitor values. in both cases, with all the sysrst pins bused together, once the turn-on sequence is complete, simultaneous shutdown upon any uvlo input failure is assured. sysrst output momentarily pulls low and turns off all gate and logic outputs. some applications may require or allow groups of supplies to be brought up in sequence and for supplies within each group to be sequenced. figure 21 shows a conf iguration that allows the first group of supplies to turn on befo re the second group starts. this arrangement does not necessarily preclude adding the assurance of all supplies prio r to turn-on sequencing, as previously shown. it does prevent the turn-on sequence from completing, if there is one unsatisfied uvlo input in a group. this configuration involves waiting through the t uvlodel and t rst del (total of ~160ms) for each sequencer ic in the chain before the final reset releases. once enable on the first sequencer is de-asserted, all reset outputs quickly pull low. this allows the sequenced turn-off of this configuration to ripple through several banks as quickly as the user-programmed (by dly_off) sequence capacitors allow. again, with common bused sysrts pins, simultaneous shutdown of all gates and logic down upon an unsatisfied uvlo input is assured, once all fets or logic outputs are on. if a gate drive option ic is used to drive both fets and logic signals, then care must be taken to ensure the charged pump gate does not overdrive and damage the logic input. a simple resistor divider can be used to lower the gate to a suitable voltage for the logic input, as shown in figure 21. figure 19. isl612x and isl613x voltage compliant sequencing block diagram isl6125 enable # n+1 isl6124 enable # n isl6131 or isl6132 monitoring on all rails uvlo uvlo vmon pgood g a t e l power supply sysrst sysrst en reset reset reset o g i c oe low = reset figure 20. multiple isl612x using logic gates for voltage presence detect isl6125 enable # n+1 isl6124 enable # n uvlo uvlo g a t e l power supply sysrst sysrst en reset reset reset o g i c uvlo oe low = reset
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 19 fn9005.11 august 25, 2011 voltage tracking in some applications, voltages ma y have to track each other as they ramp up and down, whereas others may just need sequencing. in these cases, tracking can be accomplished and has been demonstrated over a wide range of load currents (1a to 10a) and load capacitances (10f to 3300f) with the isl612x family. figure 22 and figure 23 illustrate output voltage ramping tracking performance. note that differences are less than 0.5v. with the relevant gate pins tied together in a star pattern, so that resistance between any tw o gate pins is equivalent (1k to 10k), gate ramping voltage is shared. with the same or similar enough fets, this behavior is also observed. it is suggested that this circui t implementation be prototyped and evaluated for the particular expected loads prior to committing to manufacturing build. figure 21. multiple isl612x serial configuration isl6125 enable # n+1 isl6124 enable # n uvlo uvlo g a t e l power supply sysrst sysrst reset reset reset o g i c oe low = reset enable reset to logic input figure 22. output voltage on low to high tracking figure 23. output voltage on high to low tracking
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 20 fn9005.11 august 25, 2011 negative voltage sequencing the isl612x family can use the charged pump gate output to drive fets that would control and sequence negative voltages down to a nominal -5v with minima l additional external circuitry. figure 24 shows simultaneous turn-on of the 5v bipolar supplies, and then simultaneous turn-off of the +2.5v and both positive supplies after the -5v. figure 25 shows the minimal additional external circuitry to accomplish this. the 5v zener diode is used to level-shift the gate drive down by 5v to prevent premature turn-on when gate = 0v. once gate drive voltage > vz, then fet vgs > 5v, ensuring full turn-on once gate gets to vdd + 5.3v. turn-on and turn-off ramp rates can be adjusted with the fet gate series resistor value. the -v rail is sequenced normally via the dly_x capacitor value, although adjustments in prototyping should be factored in to fine-tune for actual circuit requirements. figures 26 and 27 illustrate a hi gh-accuracy -v detection circuit using the isl6131 and a low-cost, low-accuracy -v detection circuit, respectively. application considerations timing error sources in any system there are variance contributors. for the isl612x family, timing errors are mainly contributed by three sources. capacitor timing mismatch error obviously, the absolute capacitor value is an error source; thus, lower-percentage tolerance capacitors help to reduce this error source. figure 28 illustrates a difference of 0.57ms between two dly_x outputs ramping to dly_x threshold voltage. these 5% capacitors were from a common source. in applications where two or more gates or logic outputs must have concurrent transitions, it is recommended that a common gate drive be used to eliminate this timing error. figure 24. voltage sequencing figure 25. -voltage fet drive circuit isl612x gate -v in -v out d1 r1 additional 2 components necessary for -v control and sequencing. d1 necessary to prevent premature turn-on. r1 is used to hold fet vgs = 0v until d1 vz is overcome. r1 value can be changed to adjust -v ramp rates. choose an r1 value between 4mw and 10mw initially, and fine-tune resistor value for the particular need. figure 26. high accuracy -v lock out figure 28. capacitor timing mismatch isl6131 or isl6536a -v +v to uvlo of isl612x for -v control and sequencing r1 r2 r3 r4 r5 r6 r1 and r2 define -v uvlo level. r3 ensures supervisor (isl6131 or isl6536a) pgood pull-up. r4 and r5 provide q1 gate bias between 0v and +v q1 si1300dl -bias vmon pgood +bias (1k) (10k) (15k) to 0v (resistor values suitable for -v = -5v and +v = +3.3v). or equiv. +v -v to uvlo of isl612x for control and sequencing of -v r1 r2 choose r1 and r2 values to drive uvlo high when -v is sufficiently present. figure 27. low accuracy -v presence detection
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 21 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn9005.11 august 25, 2011 for additional products, see www.intersil.com/product_tree dly_x threshold voltage and charging current mismatch the two other error sources come from the ic itself and are found across the four dly_x outputs. these errors are the dly_x threshold voltage (dly_vth) variance when the gate_x charging and discharging current latches are set, and the dly_x charging current (dly_ichg) variances to determine the time to next sequencing event. both of these parameters are bounded by specification. figure 29 shows that, with a common capacitor, the typical error contributed by these factors is insignificant, since both dly_x traces overlay each other. figure 29. dly_vth and dly_ichg timing mismatch
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 22 fn9005.11 august 25, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, re lated documentation and related parts, plea se see the respective device information pages on intersil.com: isl6123 , isl6124 , isl6125 , isl6126 , isl6127 , isl6128 , isl6130 . to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff. fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 5/24/2011 fn9005.11 - on page 1, features: added "enable" to active high information for isl6123 and isl6130. - on page 2, ordering information table: updated evaluation board; changed isl612xseqeval1z to isl6123eval1z. removed obsolete parts: isl6123ir, isl6124ir, isl6125ir, isl6126ir, isl6127ir, isl6128ir. - on page 4, pin descriptions: chan ged description for enable/enable pins from ?isl6123, isl6124, isl6125, isl6126, isl6127 and isl6130 have enable.? to ?isl6123 and isl6130 have enable, and isl6124, isl6125, isl6126 and isl6127 have enable .? - on page 6, thermal information: changed theta-ja from 48 to 46; changed theta-jc from 9 to 8. - on page 6, electrical specifications: added "isl61 25 open drain" specs for "open drain on resistance". - on page 11: changed heading "using the isl612xs eqeval1z platform" to "using the isl6123eval1z platform" and edited this section to reflec t attributes of revised evaluation board. - on page 14: replaced figure 16, "eval boar d channel 1 schematic and isl612xseqeval1z photograph" with "isl6123eval 1z schematic and photograph" - on page 16: replaced table 2, "isl612xseqeva l1z board channel 1 component listing" with "isl6123eval1z board component listing" 10/15/2008 fn9005.10 corrected pinout information in table and diagram. 2/27/2008 fn9005.9 - updated evaluation boards discussion to indicate pb -free versions throughout document. - clarified pinouts and pin description tables. - added pb-free reflow link to thermal information. 2/5/2007 fn9005.8 added isl6130 to datasheet. 10/12/2006 fn9005.7 made corrections and clarificat ions to discussions of evaluation board. 3/9/2006 fn9005.6 clarified block diagram and applications text. 12/2/2005 fn9005.5 - clarified text of sysrst functional description. - added bias and several sysrst# and rst# typical parameters numbers. - cleared up tracking scope shot mismatch. 6/10/2005 fn9005.4 improved esd to 2.5kv. 8/18/2004 fn9005.3 added pb-free options. 1/14/2004 fn9005.2 minor edits 10/3/2003 fn9005.1 minor edits 7/15/2003 fn9005.0 new document
isl6123, isl6124, isl6125, isl6126, isl6127, isl6128, isl6130 23 fn9005.11 august 25, 2011 package outline drawing l24.4x4 24 lead quad flat no-lead plastic package rev 4, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 10 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 10 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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